1. Field of the Invention
The invention relates to a pipelined data processing circuit comprising
a first register, PA1 a cascade of at least three stages, the first register being coupled to an input of the cascade, PA1 each stage comprising an input, an output, a combinatorial circuit part and a register, the input being coupled to the output via the combinatorial circuit part and the register successively, the output of each stage except a final stage being coupled to the input of a next stage in the cascade, PA1 clock means coupled to the registers, for controlling latching of data samples into the registers, data samples being latched once every cycle of a clock signal, the first register and the register in the final stage of the cascaded latching data samples in substantially the same phase of the cycle, the registers in the other stages of the cascade latching data samples at mutually different intermediate phases.
2. Description of The Related Art
Such a pipelined data processing circuit is known from U.S. Pat. No. 4,839,604.
Pipelining is a technique for increasing the sample rate at which data can be processed. Pipelining involves subdividing the combinatorial logic circuit into a cascade of combinatorial logic circuit parts separated from each other by registers. The registers are clocked in phase with each other, a sample of the data being latched into the registers once every cycle of the clock signal. During the cycle, each combinatorial circuit part computes output data as a function of its input data (this will be referred to as propagation of the data). The duration of the cycle has to be as least as long as the time-interval that the slowest combinatorial circuit part needs to compute output data as a function of its input data. This time-interval is much less than the time-interval needed for output data computation by the entire combinatorial circuit.
Pipelining has the additional advantage that it reduces power consumption. This is because pipelining reduces the number of glitches, i.e. pairs of logically meaningless, mutually opposite level transitions at the outputs of logic gates in the combinatorial circuit. Glitches may be caused as follows. The combinatorial circuit may have different circuit branches connected in parallel between an input and a multi-input logic gate, like a NAND gate. If the propagation delay time along the different circuit branches differs too much, data from the different branches may cause separate transitions at the output of the multi-input logic gate. These transitions have no independent meaning: they are glitches. When the part of the combinatorial logic circuit between successive registers is short, the differences in propagation delay will so small that the output of the multi-input logic gate will not exhibit glitches.
Pipelining has the disadvantage that it increases latency. The latency of the circuit is the number of clock cycles between the arrival of data at the input of the circuit and its arrival at the output. Latency is proportional to the number of registers in the circuit. Latency is particularly inconvenient when the circuit contains a feedback loop: the risk of instability of such loops increases as latency increases.